For the RBF stencil size a common heuristic is to use twice the number of polynomials terms. This heuristic originates from the work of Grady Wright. While this rule of thumb is a standard starting point for stencil sizing, the relationship between accuracy, computational time, and monomial augmentation remains an active area of research. Readers can find more information in the analysis by Jančič, Slak, and Kosec (2021) and citing works.

The tables below show how the RBF-FD matrix dimensions varies for 2-D and 3-D RBF-FD approximation. We also include the storage size of the matrices for 32- and 64-bit floats.

2-D RBF-FD approximation

3-D RBF-FD approximation

When computing the RBF-FD approximation weights via LU factorization or other forms of factorization (i.e. block Cholesky) the matrix will reside in the L1 or L2 cache. The maximum matrix size that fits in cache also depends on the number of right-hand sides (operators) being solved simultaneously, as those vectors must also share the cache.

Here are the L1 data cache sizes of a few recent CPU architectures:

The figure below plots the matrix storage against polynomial order up to 12, with the L1 data cache sizes drawn as horizontal references. Storage scales with the square of the number of polynomial terms, so the vertical axis is logarithmic.

For polynomials below order 7 in 2D (or 5 in 3D) the RBF-FD matrices fit comfortably in the lowest cache level. The Apple M-series and recent ARM servers like the Nvidia Grace or Fujitsu A64FX have a slight advantage due to the larger L1 cache sizes. Intel and AMD CPUs used 32 KB L1 data caches for more than a decade. AMD increased the size only recently with the Zen 5 series launched in 2024. Intel made the upgrade from 32 KB to 48 KB in the Sunny Cove architecture launched in 2019.

(Note: Apples’s efficiency cores (E-cores) use smaller 64 kB L1D caches. Intel’s efficiency cores have remained at 32 kB L1 data caches. )